The present invention relates to a transmission gate and, more particularly, to a transmission gate having a so-called body effect compensation circuit.
In a semiconductor integrated circuit, a transmission gate is used as a bus exchanger for switching transfer of signals between buses. To decrease the ON resistance of a CMOS transmission gate, addition of a body effect compensation circuit is proposed in the following reference:
Yasoji Suzuki, "How To Use CMOS Circuit (1)", Kogyo Chosakai Publishing Co., Ltd., pp. 92-93, FIG. 4.18.
The body effect is a phenomenon that, as for, e.g., an nMOS transistor, the potential difference Vbs between the back-gate voltage Vb and the source potential Vs is negatively changed by the voltage of an input signal to increase the threshold voltage, and as for a pMOS transistor, the potential difference Vbs is positively changed to increase the threshold voltage. Upon occurrence of this phenomenon, a value obtained by subtracting the threshold voltage from the voltage across the gate and source decreases, the driving ability of the n-channel MOS transistor decreases, and the signal transfer resistance increases.
A gate prepared by adding a body effect compensation circuit to an nMOS transistor that is disclosed in the above reference is a unilateral transmission gate. FIG. 8 shows a bilateral transmission gate to which a similar body effect compensation circuit is added. The drain and source of a p-channel MOS transistor P1 and those of an n-channel MOS transistor N1 are parallel-connected between bilateral input/output terminals A and B. The conductive states of the transistors P1 and N1 are controlled by an externally input enable signal /EN. An enable signal VGP inverted by an inverter INV1 is input to the gate of the transistor P1, whereas an enable signal /VGN inverted by the inverter INV1 and an inverter INV2 is input to the gate of the transistor N1. Upon reception of a high-level enable signal /EN, both the transistors P1 and N1 are turned on to render the input/output terminals A and B conductive.
A p-well Pw where the n-channel MOS transistor N1 is formed, and a p-well Pw where n-channel MOS transistors N1N and N2N are formed are the same or electrically connected to each other. With this structure, the back gate Pw of the transistor N1 and the back gates of the transistors N1N and N2N have the same potential. The drains and sources of the transistors N1N and N2N are series-connected between the input/output terminals A and B. The drain and source of the transistor N1N are connected to those of a p-channel MOS transistor P1N, and the drain and source of the transistor N2N are connected to those of a p-channel MOS transistor P2N. The enable signal /VGN is input to the gates of the transistors N1N and N2N, while the enable signal VGP is input to the gates of the transistors P1N and P2N. The drain of a transistor N2 is connected to the back gate Pw of the transistor N1, its gate receives the enable signal VGP, and its source is grounded.
More specifically, as shown in FIG. 9, the p-well Pw and an n-well Nw are formed in the surface of an n-type semiconductor substrate 101. N-type diffusion layers ND1 of the n-channel MOS transistors N1, N1N, and N2N are formed in the same p-well Pw or separate p-wells Pw electrically connected to each other. N-type diffusion layers of the n-channel MOS transistors N2 is formed in a p-well being electrically independent on the p-well for n-channel MOS transistors N1, N1N, N2N. P-type diffusion layers PD3 of the p-channel MOS transistors P1, P1N, and P2N are formed in the same n-well Nw or separate n-wells Nw electrically connected to each other. The potential of the n-well Nw must be set to the power supply voltage Vcc, and is applied with the voltage Vcc via n-type diffusion layers ND2 and ND3. The potential of the p-well Pw for the n-channel MOS transisters N1, N1N, N2N need not be set to the ground voltage, and is applied with a voltage Vpw corresponding to an input voltage to the transmission gate via p-type diffusion layers PD1 and PD2. In contrast, the p-well for the n-channel MOS transistor N2 is set to the ground potential.
In the n-channel MOS transistors N1, the potential difference between the back gate and the source can be set to almost 0 by the body effect compensation circuit, and the above-described body effect can be compensated. As for the p-channel MOS transistor P1, however, no body effect can be compensated because the back gate is fixed to the power supply voltage Vcc.
If an n-well is formed in a p-type semiconductor substrate in contrast to the circuit shown in FIGS. 8 and 9, a body effect compensation circuit made up of p-channel MOS transistors P1P and P2P formed in the same n-well Nw or electrically connected n-wells Nw, and nMOS transistors N1P and N2P can be added to only the p-channel MOS transistor P1, as shown in FIG. 10. As for the n-channel MOS transistor N1, no body effect is compensated.
FIG. 11 shows a semiconductor substrate 111 having a triple well structure. A deep n-well D-Nw is formed in the surface of the p-type semiconductor substrate 111, and a p-well D-Pw is formed in the surface of the n-well D-Nw. An n-channel MOS transistor is formed in the p-well D-Pw. A p-well Pw is formed in the surface of the semiconductor substrate 111, and an n-well Nw is formed in the surface of the p-well Pw. P-type diffusion layers PD13 of a p-channel MOS transistor are formed in the n-well Nw.
The outer n-well D-Nw is set to the power supply voltage Vcc, and the p-well Pw is grounded. The potential of the p-well D-Pw in the n-well D-Nw is set to a voltage Vdpw on the ground potential corresponding to an input voltage, and the potential of the n-well Nw in the p-well Pw is similarly set to a voltage Vnw or the power supply voltage Vcc corresponding to an input voltage. With this structure, the back gate of the n-channel MOS transistor need not be set to the ground potential, and the back gate of the p-channel MOS transistor need not be set to the power supply voltage Vcc, either. In this structure, as shown in FIG. 12, p-channel MOS transistors P1P, P2P and P2 and n-channel MOS transistors N1P and N2P constitute a body effect compensation circuit for a p-channel MOS transistor P1, whereas n-channel MOS transistors N1N, N2N and N2 and p-channel MOS transistors P1N and P2N constitute a body effect compensation circuit for an n-channel MOS transistor N1. In this circuit arrangement, the drain of a p-channel MOS transistor P2 is connected to the back gate Nw of the transistor P1, its gate receives a gate signal VGN, and its source is connected to the power supply voltage Vcc terminal. The drain of an n-channel MOS transistor N2 is connected to the back gate Pw of the transistor N1, its gate receives a signal VGP, and its source is grounded.
In the arrangement shown in FIG. 12, however, the following phenomenon occurs. The back gates of the n-channel MOS transistors N1P and N2P are fixed to the ground potential, and the back gates of the p-channel MOS transistors P1N and P2N are fixed to the voltage Vcc. Accordingly, the four transistors are affected by the body effect to decrease their driving abilities and increase their signal transfer resistances. This decreases the transfer speed of the potential at the input/output terminal A or B to the back gate Nw of the p-channel MOS transistor P1 and the back gate Pw of the n-channel MOS transistor N1. That is, when a signal is input to the input/output terminal A or B, the rate of change in back-gate potential which follows the potential of this signal decreases, and a potential between the backgate and the source occurs, so that the body effect transitionally acts on the p-channel MOS transistor P1 and the n-channel MOS transistor N1. As a result, the signal transfer speed from the input/output terminal A or B to the input/output terminal B or A decreases.
As described above, in the transmission gate, the signal transfer speed decreases owing to the body effect.